The present invention relates generally to semiconductor device manufacturing and, more particularly, to improved integration of passive device structures with metal gate layers.
In standard complementary metal oxide semiconductor (CMOS) devices, polysilicon is typically used as the standard gate material. The technology of fabricating CMOS devices using polysilicon gates has been in a constant state of development, and is now widely used in the semiconductor industry. One advantage of using polysilicon gates is that they can sustain high temperatures. However, there are also some problems associated with using a polysilicon gate. For example, due to the poly-depletion effect, polysilicon gates commonly used in CMOS devices are becoming a gating factor in chip performance for channel lengths of 0.1 micron and below. Another problem with polysilicon gates is that the dopant material in the polysilicon gate (e.g., boron) can easily diffuse through the thin gate dielectric causing further degradation of the device performance. Thus, one proposed way of improving the performance of sub-micron transistors is to use metal gates in place of conventional polysilicon gates, particularly with the advent of high-k gate dielectric materials.
In addition to transistor devices, other types of devices are also formed on integrated circuits. For example, certain passive device structures such as resistors and eFUSEs are formed above the substrate level. In particular, where such devices are integrated with metal gate technology, a silicon layer is formed on top of the metal gate layer (used in forming the metal gates in the transistor region). Thus, while the metal gate layer located in the transistor or active device regions is patterned according to a desired gate structure, the other portions of the metal gate layer residing in the passive device regions remain unpatterned and permanently reside below the passive device structures.